Closed Form Solution for Delay and Power for a Cmos Inverter Driving Rlc Interconnect under Step Input
نویسندگان
چکیده
In this paper, a closed form delay and power model of a CMOS inverter driving a resistive-inductive-capacitive load is presented. The model is derived from Sakurai’s alpha-power law and exhibits good accuracy. The model can be used for the design and analysis of the CMOS inverters that drive a large interconnect RLC load when considering both speed and power. Closed form expressions are also presented for the propagation delay and transition time which exhibit less than 15% error compared to the SPICE for a wide range of RLC loads. Explicit methods are also provided for modelling the short-circuit power dissipation of a CMOS inverter driving a RLC line. The average error is within 22% compared to SPICE for most practical loads. The resistive power dissipation has also been considered for various RLC loads which are accurate to within 9% to that of SPICE.
منابع مشابه
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